| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst7 |
5 |
3 |
0 |
3 |
7 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst2 |
5 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst47 |
4 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst21|LPM_MUX_component|auto_generated |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst21 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst46 |
22 |
0 |
1 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst6 |
5 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst51 |
1 |
1 |
0 |
1 |
5 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst45 |
4 |
2 |
0 |
2 |
16 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst36 |
19 |
2 |
0 |
2 |
6 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst44 |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst3|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst3 |
1 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_003|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_003|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_003 |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_002|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_002|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_002 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_001|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller_001 |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|rst_controller |
33 |
31 |
0 |
31 |
1 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| inst|irq_synchronizer_002 |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|irq_synchronizer_001 |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|irq_synchronizer |
5 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|irq_mapper |
5 |
29 |
2 |
29 |
32 |
29 |
29 |
29 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_012|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_012 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_011 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_009 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_006 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
22 |
1 |
2 |
1 |
21 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_004 |
22 |
0 |
0 |
0 |
21 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_017|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_017|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_017|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_017 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_016|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_016|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_016|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_016 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_015|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_015|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_015|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_015 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_014|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_014|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_014|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_014 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_013|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_013|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_013|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_013 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_012|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_012|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_012|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_012 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_011|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_011|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_011|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_011 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_010|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_010|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_010|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_010 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_009|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_009|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_009|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_009 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_008|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_008|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_008|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_008 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_007|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_007|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_007|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_007 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_006|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_006|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_006|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_006 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_005|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_005|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_005|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_005 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_004|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_004|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_004|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_004 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_003|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_003|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_003|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_003 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_002|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_002|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_002|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_002 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_001|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_001|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_001|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser_001 |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser|clock_xer |
131 |
0 |
0 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|crosser |
133 |
2 |
0 |
2 |
127 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_cmd_width_adapter |
132 |
3 |
0 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_cmd_width_adapter |
132 |
3 |
0 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_cmd_width_adapter |
132 |
3 |
0 |
3 |
109 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_rsp_width_adapter|uncompressor |
48 |
4 |
0 |
4 |
39 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_rsp_width_adapter |
114 |
3 |
0 |
3 |
127 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_rsp_width_adapter|uncompressor |
48 |
4 |
0 |
4 |
39 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_rsp_width_adapter |
114 |
3 |
0 |
3 |
127 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_rsp_width_adapter|uncompressor |
48 |
4 |
0 |
4 |
39 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_rsp_width_adapter |
114 |
3 |
0 |
3 |
127 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001|arb|adder |
20 |
10 |
0 |
10 |
10 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001|arb |
9 |
0 |
4 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux_001 |
633 |
0 |
0 |
0 |
131 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux|arb|adder |
52 |
26 |
0 |
26 |
26 |
26 |
26 |
26 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux|arb |
17 |
0 |
4 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_mux |
1641 |
0 |
0 |
0 |
139 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_012 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_011 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_010 |
130 |
4 |
2 |
4 |
253 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_009 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_008 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_007 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_006 |
130 |
4 |
2 |
4 |
253 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_005 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_004 |
130 |
4 |
2 |
4 |
253 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_003 |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_002 |
130 |
4 |
2 |
4 |
253 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux_001 |
130 |
4 |
2 |
4 |
253 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|rsp_demux |
129 |
1 |
2 |
1 |
127 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_012 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_011 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_010|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_010|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_010 |
255 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_009 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_008 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_007 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_006|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_006|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_006 |
255 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_005 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_004|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_004|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_004 |
255 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_003 |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_002 |
255 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux_001 |
255 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_mux |
129 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_demux_001 |
133 |
25 |
2 |
25 |
631 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|cmd_demux |
141 |
169 |
2 |
169 |
1639 |
169 |
169 |
169 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
111 |
6 |
8 |
6 |
109 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_burst_adapter |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
111 |
6 |
8 |
6 |
109 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_burst_adapter |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_burst_adapter|altera_merlin_burst_adapter_uncompressed_only.burst_adapter |
111 |
6 |
8 |
6 |
109 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_burst_adapter |
111 |
0 |
0 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_014|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_014 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_013|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_013 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_012|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_012 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_011|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_011 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_010|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_010 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_009|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_009 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_008|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_008 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_007|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_007 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_006|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_006 |
98 |
0 |
2 |
0 |
109 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_005|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_005 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_004|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_004 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_003|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_003 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_002|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_002 |
116 |
0 |
2 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_001|the_default_decode |
0 |
17 |
0 |
17 |
17 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router_001 |
116 |
0 |
6 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router|the_default_decode |
0 |
17 |
0 |
17 |
17 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|router |
116 |
0 |
6 |
0 |
127 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_1_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_1_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_1_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_1_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_0_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_0_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_0_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_0_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_agent |
250 |
22 |
34 |
22 |
266 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_1_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_1_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_1_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_1_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_0_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_0_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_0_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_0_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_agent_rdata_fifo |
63 |
41 |
0 |
41 |
20 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_agent |
250 |
22 |
34 |
22 |
266 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|timer_s1_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|timer_s1_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|timer_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|timer_s1_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_agent_rsp_fifo |
138 |
39 |
0 |
39 |
97 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_agent |
250 |
22 |
34 |
22 |
266 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|altpll_0_pll_slave_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|altpll_0_pll_slave_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|altpll_0_pll_slave_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|altpll_0_pll_slave_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_debug_mem_slave_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_debug_mem_slave_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_debug_mem_slave_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_data_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_data_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_data_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_data_agent |
318 |
39 |
50 |
39 |
340 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_csr_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_csr_agent_rsp_fifo |
156 |
39 |
0 |
39 |
115 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_csr_agent|uncompressor |
48 |
1 |
0 |
1 |
46 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_csr_agent |
318 |
39 |
50 |
39 |
337 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_instruction_master_agent |
201 |
42 |
95 |
42 |
148 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_data_master_agent |
201 |
42 |
95 |
42 |
148 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_1_s1_translator |
96 |
22 |
45 |
22 |
57 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|uart_0_s1_translator |
96 |
22 |
45 |
22 |
57 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_memory_s1_translator |
112 |
7 |
14 |
7 |
88 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|spi_master_0_s1_translator |
77 |
6 |
26 |
6 |
40 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_1_s1_translator |
112 |
6 |
30 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|pio_0_s1_translator |
112 |
6 |
30 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|sdram_s1_translator |
77 |
4 |
4 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|timer_s1_translator |
96 |
22 |
45 |
22 |
55 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|dpr_memory_s1_translator |
77 |
7 |
16 |
7 |
52 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|altpll_0_pll_slave_translator |
112 |
6 |
27 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_debug_mem_slave_translator |
112 |
5 |
20 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_data_translator |
115 |
4 |
10 |
4 |
91 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|onchip_flash_0_csr_translator |
112 |
6 |
28 |
6 |
69 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_instruction_master_translator |
113 |
51 |
0 |
51 |
105 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0|nios2_data_master_translator |
113 |
12 |
0 |
12 |
105 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| inst|mm_interconnect_0 |
429 |
0 |
0 |
0 |
537 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_1|the_RL02_System_uart_1_regs |
41 |
0 |
0 |
0 |
47 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_1|the_RL02_System_uart_1_rx|the_RL02_System_uart_1_rx_stimulus_source |
21 |
0 |
20 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_1|the_RL02_System_uart_1_rx |
23 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_1|the_RL02_System_uart_1_tx |
31 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_1 |
26 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_0|the_RL02_System_uart_0_regs |
41 |
12 |
6 |
12 |
43 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_0|the_RL02_System_uart_0_rx|the_RL02_System_uart_0_rx_stimulus_source |
17 |
0 |
16 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_0|the_RL02_System_uart_0_rx |
19 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_0|the_RL02_System_uart_0_tx |
27 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|uart_0 |
26 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|timer |
23 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|spi_master_0|inst_spi |
25 |
0 |
2 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|spi_master_0 |
25 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|sdram|the_RL02_System_sdram_input_efifo_module |
48 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|sdram |
48 |
1 |
1 |
1 |
40 |
1 |
1 |
1 |
16 |
0 |
0 |
0 |
0 |
| inst|pio_1 |
62 |
0 |
8 |
0 |
56 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|pio_0 |
54 |
0 |
16 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory|the_altsyncram|auto_generated|mux2 |
130 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory|the_altsyncram|auto_generated|decode3 |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory|the_altsyncram|auto_generated |
54 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_memory |
58 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|altera_onchip_flash_block |
34 |
2 |
0 |
2 |
36 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller|sector_convertor |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller|sector_address_write_protection_checker |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller|access_address_write_protection_checker |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller|address_convertor |
23 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller|address_range_checker |
23 |
4 |
0 |
4 |
1 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_data_controller |
127 |
6 |
6 |
6 |
76 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0|avmm_csr_controller |
47 |
4 |
4 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| inst|onchip_flash_0 |
94 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_debug_slave_wrapper|the_RL02_System_nios2_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_debug_slave_wrapper|the_RL02_System_nios2_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_ocimem|RL02_System_nios2_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_ocimem|RL02_System_nios2_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_avalon_reg |
48 |
0 |
28 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_fifo|the_RL02_System_nios2_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_fifo|the_RL02_System_nios2_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_fifo|the_RL02_System_nios2_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_dtrace|RL02_System_nios2_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_dtrace |
114 |
0 |
103 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_itrace |
24 |
53 |
24 |
53 |
53 |
53 |
53 |
53 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_dbrk |
99 |
0 |
0 |
0 |
103 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_xbrk |
65 |
5 |
62 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci|the_RL02_System_nios2_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_nios2_oci |
178 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|RL02_System_nios2_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|RL02_System_nios2_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|RL02_System_nios2_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|RL02_System_nios2_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu|the_RL02_System_nios2_cpu_test_bench |
321 |
3 |
287 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2|cpu |
149 |
1 |
29 |
1 |
133 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|nios2 |
149 |
0 |
0 |
0 |
131 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|dpr_memory|the_altsyncram|auto_generated |
68 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|dpr_memory |
75 |
1 |
2 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|altpll_0|sd1 |
3 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inst|altpll_0|stdsync2|dffpipe3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|altpll_0|stdsync2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inst|altpll_0 |
48 |
39 |
30 |
39 |
35 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| inst |
82 |
5 |
0 |
5 |
85 |
5 |
5 |
5 |
16 |
0 |
0 |
0 |
0 |
| inst5 |
9 |
4 |
0 |
4 |
38 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |