// This module provides the necessary timing for the MFM
// ENcoder and the shiftregister timing. The shiftregister
// logic works like a 74166. A full verilog Version of a 
// MFM ENcoder ist implemented in "my_MFM_ENcoder_V1_x."
//
//    by: Reinhard Heuberger , www.PDP11GY.com, JUL, 2011
//
module myloader(
       clk50,               // 50Mhz clock
       enable,              // Enable
       clk_16_4,            // Input Clock  16.4 MHz
       go_sector,
       //
       clk_8_2,             // Out-Clock 8.2MHz
       clk_4_1,             // Out-Clock 4.1MHZ
       clk_16bit,           // Out-clock, 16Bit 
       load_L,              // Shiftregister LOAD_L
       load_clk );          // and Loaad clock pulse.
//
input	clk50, enable, clk_16_4, go_sector;
output	load_L, load_clk,clk_8_2, clk_4_1, clk_16bit;
//
reg [2:0] shift;
reg [5:0] divider;
//
// 
// The clock input is 16.4 MHz to get the double frequency of
// 8.2 MHz, necessary for MFM phase shifting. The 16bit tranfer
// rate runs at 256.25KHz. 
//
always @(posedge clk_16_4)
begin
  //
  if (enable && go_sector)
    begin
     divider <= divider - 1;
    end
  else if (!go_sector) begin
   divider <= 0;
  end
  //
end
assign clk_8_2 =   divider[0];  // Output: 8.2Mhz
assign clk_4_1 =   divider[1];  // Output: 4.1MHz
assign clk_16bit = divider[5];  // Output 16Bit Clock
//
//
// Generate a laod-enable_L singnal and 400ns Clockpulse 
// for (re)loading the shiftregister.
//
always @(posedge clk50)
begin
 shift = shift << 1;
 shift[0] = clk_16bit;
end
//
assign	load_clk =  ((shift[0] ^ shift[1]) & clk_16bit);
assign	load_L   = ~((shift[2] ^ clk_16bit) & clk_16bit);
//
endmodule