' MFM DECODER ( DPLL ) algorithm by Reinhard Heuberger ' ' This Code is represent for the DEC RL02 disk drive which runs at a ' data transfere rate with 4.1 MHz. ' Counting the MFM signals periods with a 50MHz FPGA will provide following results: ' short MFM cycle-period , 0.250uS = count value 12 ' long MFM cycle-period , 0,375uS = count value 18 ' very-long MFM cycle-period , 0,500uS = count value 24 ' ' mfm!=FALSE mfmlong%=0 RESTORE mfmcode DO // ***** this DO-loop represents a couter ****** READ mfmpulse% // ***** to receive the MFM puls periods ****** EXIT IF mfmpulse%=0 IF mfmpulse%=-1 // \ PRINT "" // \ READ a$ // \ PRINT "Soll: ";a$ // Read and handle PRINT "Ist: "; // the test pattern mfm!=FALSE // / READ mfmpulse% // / ENDIF // / ' ' ******************************************************************** ' ********************** MFM DECODER ALGORITHM *********************** ' IF mfmpulse% > 12 IF mfmpulse% > 18 // Very-Long cyclus , 0.500uS PRINT "10"; // Always Output 2 Bits, sequenze "10" mfmlong%=0 // Reset Long-Cycle-Flag ELSE // Long cyclus , 0.375uS SELECT mfmlong% CASE 0 // *** FIRST Entry Long-Cycle *** PRINT ABS(mfm!); // Output current value IF mfm!=FALSE // IF we have the MFM douple "00" PRINT ABS(mfm!); // than recover this MFM feature ENDIF mfm!=NOT(mfm!) // FLIP Bit mfmlong%=1 // SET Long-Cycle-Flag CASE 1 // *** Long-Cycle loop, phase #1 *** PRINT ABS(mfm!); IF mfm!=FALSE // IF we have the MFM douple "00" PRINT ABS(mfm!); // than recover this MFM feature ENDIF mfm!=NOT(mfm!) // FLIP Bit mfmlong%=2 // Set Long-Cycle-Flag for phase #2 CASE 2 // *** Long-Cycle loop, phase #2 *** PRINT ABS(mfm!); // Output prepared value PRINT ABS(mfm!); // Output current value mfm!=NOT(mfm!) // FLIP Bit mfmlong%=1 // Set Long-Cycle-Flag back for phase #1 ENDSELECT ENDIF ELSE // Short cyclus, 0.250uS PRINT ABS(mfm!); // Output current value mfmlong%=0 // Reset Long-Cycle-Flag ENDIF ' '********************************************************************** LOOP PRINT " End:=press key"; INPUT x$ ' mfmcode: DATA -1 DATA "0) 00001111000100111010101011" DATA 12,12,18,12,12,12,18,12,18,18,18,12,12,24,24,24,24,12,12 DATA -1 ' DATA "1) 0000111111110000000011111111000000001" DATA 12,12,18,12,12,12,12,12,12,12,18,12,12,12,12,12,12,18 DATA 12,12,12,12,12,12,12,18,12,12,12,12,12,12,18,12 DATA -1 ' DATA "2) 0000110011001100110011001" DATA 12,12,18,12,18,18,12,18,18,12,18,18,12,18,18,12,18,18,12 DATA -1 ' DATA "3) 00001010101010111" DATA 12,12,18,24,24,24,24,24,12,12,12 DATA -1 ' DATA "4) 000010010010010010010010011" DATA 12,12,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,12,12 DATA -1 ' DATA "5) 000011000100100010010011101111" DATA 12,12,18,12,18,12,18,18,18,18,12,18,18,18,18,18,12,12,24,12,12,12,18 DATA -1 ' DATA "6) 00001000000010000000100" DATA 12,12,18,18,12,12,12,12,12,18,18,12,12,12,12,12,18,18,12,12 DATA -1 ' DATA "7) 000011100111001110011100" DATA 12,12,18,12,12,18,18,12,12,18,18,12,12,18,18,12,12,18,18 DATA -1 ' DATA "8) 0000110001100011000110001111" DATA 12,12,18,12,18,12,18,12,18,12,18,12,18,12,18,12,18,12,18,12,12,12,18 DATA -1 ' DATA "9) 0000111111101111111011111110" DATA 12,12,18,12,12,12,12,12,12,24,12,12,12,12,12,12,24,12,12,12,12,12,12,24 ' DATA 0 ---------------------------------------------------------------------------------------- Output: Soll: 0) 00001111000100111010101011 Ist: 00001111000100111010101011 Soll: 1) 0000111111110000000011111111000000001 Ist: 0000111111110000000011111111000000001 Soll: 2) 0000110011001100110011001 Ist: 0000110011001100110011001 Soll: 3) 00001010101010111 Ist: 00001010101010111 Soll: 4) 000010010010010010010010011 Ist: 000010010010010010010010011 Soll: 5) 000011000100100010010011101111 Ist: 000011000100100010010011101111 Soll: 6) 00001000000010000000100 Ist: 00001000000010000000100 Soll: 7) 000011100111001110011100 Ist: 000011100111001110011100 Soll: 8) 0000110001100011000110001111 Ist: 0000110001100011000110001111 Soll: 9) 0000111111101111111011111110 Ist: 0000111111101111111011111110