and Project Completion
RL01/RL02 FPGA based Disk-Emulator
operation of the RL01/RL02 Emulator is best
with a VIDEO
in the first version, based on the DE1-Board.
cooperation with Computer
and completion of a PCB board for the RL01/RL02 disk emulator
User Manuel: README
DE10-Lite user , a start-up Manuel:
bootable RT-11 RL-emulator images ( dl0,dl2,dl3):
Circuit diagram and layout information: RL_Emulator_v2_1
diagram and layout information: RL_Emulator_v2_2
questions, please send an e-mail to: RLEMU@cm-muenchen.de
Flash and c-programs
emulator interface works with any of the following FPGA
The entire software
was completed with Quartus version
each FPGA board a flash
available to start the respective board immediately.
quick start, a manual is included as a readme file.
note: The entire project is open
therefore a project folder is also available.
you to flash the firmware with a jic-file or pof-file (DE10). The
c-programs can be edited or modified via
without problems. However, the firmware/verilog source
are missing. We are happy to provide these programs by e-mail. We
just want to know who gets these programs and how the plans are
for using all these firmware sources. Cooperation is really
important to us!
Please send e-mail to:
/ DE10-Lite Implementierung
memory, emulates simultaneously up to 4 RL01 or RL02 disk drives.
up to 4 RL01 or RL02 disk drives, sorry,
not available at the moment ?? (MAY 2017)
interface also works with this
old DE1 board but there are some limitations due to the only 8MB
SDRAM memory: - Only support of one RL01 disk drive. RL02 support
not possible. - No FAT32 support for the SD-Card and incompatible
file format. For
further questions about this DE1 configuration, please send an
is the configuration based on the DE0-Nano-SoC board. It will
probably be available in early of 2018 in the first version.
It is the ideal board because it can also be
used for other purposes such as PDP-11 and PDP-8 emulators.
However, a lot of issues must be new developed.
A NIOS II CPU with the existing C-code is very difficult to
implement here, so everything has to be ported to the ARM
Cortex-A9 CPU environment. If someone has already experience with
this environment I would be glad about a contact very much.
Perhaps it is also an interesting challenge for
a student? Cooperation is very important.
the end, this was my last wire wrap work.