1.1B STATUS and Project Completion

DEC RL01/RL02 FPGA based Disk-Emulator

The operation of the RL01/RL02 Emulator is best viewed with a VIDEO via YouTube, however, in the first version, based on the DE1-Board.

In cooperation with Computer Museum Muenchen
Development and completion of a PCB board for the RL01/RL02 disk emulator

Further informations:
A detailed description, User Manuel: README
For DE10-Lite user , a start-up Manuel: Getting_Started
3 bootable RT-11 RL-emulator images ( dl0,dl2,dl3): emulator-images
Convert/verify .DSK <==>.DEC files: RL_tools
Circuit diagram and layout information:
Circuit diagram and layout information: RL_Emulator_v2_2
For questions, please send an e-mail to:

Firmware/Verilog, Flash and c-programs

@ GitHub

Support SELECT and WLAN Mode
Version V1.5

My recommendation :
MAX10 / DE10-Lite Implementierung
64MB memory, emulates simultaneously up to 4 RL01 or RL02 disk drives.

Flash folder, all versions: de10_flash
Project folder
@ GitHub

BeMicro CV Implementation
128MB memory, emulates simultaneously up to 4 RL01 or RL02 disk drives, sorry, not available at the moment ?? (MAY 2017)

Flash folder: BeMicro_flash
Project folder
@ GitHub

DE0-Nano Implementation
E16MB memory, emulates 1 RL01 or RL02 disk drive

Flash folder: DE0_Nano_flash
Project folder
@ GitHub

DE1 Board Implementation
emulates only 1 RL01 disk drive

Our emulator interface also works with this relatively old DE1 board but there are some limitations due to the only 8MB SDRAM memory: - Only support of one RL01 disk drive. RL02 support not possible. - No FAT32 support for the SD-Card and incompatible file format. For further questions about this DE1 configuration, please send an e-mail.

DE0-Nano-SoC Board Implementation
This is the configuration based on the DE0-Nano-SoC board. It will probably be available in early of 2018 in the first version.

It is the ideal board because it can also be used for other purposes such as PDP-11 and PDP-8 emulators. However, a lot of issues must be new developed. A NIOS II CPU with the existing C-code is very difficult to implement here, so most of all has to be ported to the ARM Cortex-A9 CPU environment.
Currently the entire firmware is successfully ported (AUG 2017).

In the end, this was my last wire wrap work.